VLSI architecture and design for high performance adaptive video scaling

In this paper, we develop an efficient architecture for video scaling based on the adaptive image scaling algorithm [3] ,[4]. We then develop the design of the computation units and perform synthesis to show that the chip area required to perform scaling from QCIF to 4CIF is about 20mm2 using 0 . 5 ~ technology. In video applications, the data rate involved is extremely high. When the available bandwidth is limited, the image size is restricted. A high-performance real time scaling technique that can scale an image while introducing little distortion will allow us to transmit video data using a small bandwidth while maintaining perceptual quality. Another motivation for developing a good scaling algorithm is to enable display of lower resolution images on higher resolution monitors (For eg., an NTSC format picture on HDTV monitors). Simple scaling techniques (such as simple pixel replication, bilinear interpolation and cubic interpolation) cause visible effects such as jagged or blurred edges when the images contain sharp edges or thin lines. Non-linear model based interpolation techniques have been proposed in [2] and [3]. However, these technique were considered difficult to implement in practical systems because of the complexity of the classification and the filtering requirements. We develop an architecture based on the algorithm in [3],[4]. Specifically, we consider an architecture for scaling QCIF images to 4CIF format at 30 frames/sec. A straightforward architecture cannot meet the speed requirements. We apply transformations to the data flow graph to obtain an efficient architecture that meets the throughput requirements. The ASIC area requirements are then estimated based on a synthesis starting from a Verilog description of the computation units.